DIGITAL DESIGN / FPGA / EMBEDDED HARDWARE

Daniel Pacheco

I’m an electrical engineer working across Verilog RTL, FPGA implementation, and circuit-card design. My projects connect digital logic and simulation with Altium schematics, embedded interfaces, and hands-on FPGA board checks.

Clemson B.S. Electrical Engineering · Engineer-in-Training · South Carolina

Daniel Pacheco

RTL / SIMULATION / FPGA IMPLEMENTATION

Digital logic & FPGA

Verilog · AMD Vivado · PYNQ-Z2 / Zynq

Built logic, adders, and ROM-based comparators; wrote a testbench covering all 16 input combinations of a 2-bit comparator. Took a 2-to-1 MUX through XDC pin constraints, synthesis, implementation, bitstream generation, and board-level switch/LED checks.

More engineering work

Embedded C & peripheral interfaces

C · SPI · GPIO · interrupts · timers / PWM

Wrote microcontroller firmware for button and timer interrupts, PWM output, and a separate SPI master exercise. Source code is linked from the project page.

Circuit modeling & simulation

Altium MixedSim · course exercise

Recreated an RC circuit tolerance study using Gaussian, uniform, and Worst Case Monte Carlo simulations, with schematic and output plots.

Selected technical training

Relevant simulator and ECAD credentials, with supporting badge images and verification links.

Engineering experience

At Santee Cooper, I ported C source from Windows to Linux, deployed version-controlled changes across eight servers using Git, and supported system integration and acceptance testing with technical documentation. These workflows reinforce the development, validation, and configuration-management side of my hardware work.