Embedded hardware PCB design
Schematic and multilayer PCB layout for assigned embedded hardware circuits: an SPI-connected IMU, a USB programming/debug interface with ESD protection, and a 44-pin expansion header.
Daniel Pacheco
I’m an electrical engineer focused on PCB design and FPGA development. I graduated from Clemson University in May 2025 and work as an Energy Management System Engineer at Santee Cooper.
My hardware work includes schematic and multilayer PCB layout in Altium for an Aeronix-sponsored senior design project. I’m also working through Verilog and Vivado labs, from testbench simulation to programming a PYNQ-Z2 board.
I’m interested in PCB design and entry-level FPGA/RTL roles.
Selected projects
Verilog and FPGA labs
Digital logic and ROM-based designs with simulation testbenches. Board exercises include a multiplexer implemented through XDC constraints, synthesis, implementation, and bitstream programming.
RC circuit Monte Carlo study
An Altium course exercise comparing the effect of component tolerances on a loaded RC circuit, using Gaussian, uniform, and Worst Case Monte Carlo simulations.
Experience
June 2025–present
Energy Management System Engineer · Santee Cooper
I work on SCADA telemetry, alarms, and system models. My responsibilities include test planning and factory acceptance testing in Jama Connect, checkouts with relay/protection teams, and troubleshooting operational data. I also develop C and Python tools for engineering workflows.
Current study
I’m continuing Altium design and simulation work alongside Verilog labs in Vivado. Recent work includes MixedSim component-tolerance analysis, ROM initialization, and FPGA simulation and implementation.