Daniel Pacheco, EIT

Electrical engineer · PCB design and FPGA development · South Carolina

danielpacheco.dev · GitHub · LinkedIn · Contact

Education

Clemson University — B.S. Electrical Engineering

May 2025 · Engineer-in-Training; FE exam passed

Coursework: digital design, computer organization, microcontroller interfacing, signal processing.

Technical skills

PCB / embedded: Altium Designer, schematic capture, multilayer PCB layout, SPI, I2C, UART, GPIO, ESD protection.

FPGA: Verilog, AMD Vivado, testbenches, behavioral simulation, synthesis, implementation, XDC pin constraints, PYNQ-Z2 / Zynq-7000.

Programming / tools: C, C++, Python, MATLAB/Simulink, Linux, Git, SQL, Jama Connect.

Relevant engineering experience

Aeronix Technologies Group / Clemson — Laboratory Assistant

January–May 2025 · Senior Design II · Clemson, SC

  • Created Altium schematics and multilayer PCB layouts for assigned embedded hardware circuits, including an LSM6DSOX 6-axis IMU over SPI with pin assignments and interrupt routing.
  • Designed a Micro-USB Type-B programming/debug interface with ESD protection and a 44-pin expansion header exposing GPIO, SPI, I2C, and UART.
  • Produced hardware documentation and supported PCB subsystem design reviews.

Santee Cooper — Energy Management System Engineer

June 2025–present · Moncks Corner, SC

  • Ported C source from Windows to Linux and compiled it for the new EMS environment; developed a C storm-response dashboard for feed and restoration tracking.
  • Deployed version-controlled changes across eight servers using Git, documented commit hashes, and supported team Git workflows for display updates.
  • Migrated more than 300 TB of historian data, imported metadata, and worked on database schemas during the EMS replacement.
  • Supported system cutover, test planning and factory acceptance testing in Jama Connect, and SCADA telemetry, alarm, and model troubleshooting.

Selected projects

Verilog and FPGA labs

Independent study · 2026

  • Developed decoders, priority encoders, adders, and ROM-based comparators in Verilog; initialized ROM with $readmemb and explored Block Memory Generator IP.
  • Exercised all 16 input combinations of a 2-bit ROM comparator in a simulation testbench. Implemented a 2-to-1 multiplexer on PYNQ-Z2 and verified switch-to-LED behavior.

RC circuit Monte Carlo study

Recreated an Altium course exercise to compare component-tolerance effects using Gaussian, uniform, and Worst Case Monte Carlo simulations.

Microcontroller peripheral labs

C firmware coursework covering GPIO, button/timer interrupts, PWM, and a separate SPI master exercise.

Training and credentials

Altium PCB Design Essentials, Skilled Engineer, and Mixed-Signal Simulation; Cadence Allegro PCB Editor Basic Techniques v22.1 and Xcelium Simulator v24.03. PCB credentials · Simulation credential.