Verilog and FPGA labs
I’m using small digital-design exercises to practice writing Verilog, checking behavior in simulation, and implementing designs on an FPGA. My recent labs cover combinational logic, ROM-based designs, and the Vivado implementation flow.
RTL and simulation
- Developed Verilog modules for decoders, priority encoders, adders, and ROM-based comparators.
- Initialized ROM contents with
$readmemband explored Vivado’s Block Memory Generator IP and COE initialization. - Wrote a testbench exercising all 16 input combinations of a 2-bit ROM comparator and inspected its outputs in Vivado behavioral simulation.
Board implementation
For a 2-to-1 multiplexer, I assigned PYNQ-Z2 pins with XDC constraints, ran synthesis and implementation, generated a bitstream, and programmed the board. I verified the switch-to-LED behavior on the hardware.
I also built a Zynq processing-system design in Vivado IP Integrator, generated the HDL wrapper and bitstream, and used the PYNQ-Z2 setup to control board LEDs.
Related work
My microcontroller labs cover peripheral configuration, interrupts, PWM, and SPI in C. My senior design PCB work covers the schematic and layout side of embedded interfaces.