Verilog and FPGA labs
- Context
- Independent study · completed labs and ongoing learning
- Tools
- Verilog · SystemVerilog · Vivado
- Hardware
- PYNQ-Z2 · Nexys A7-100T
My completed labs cover Verilog logic and memory designs, simulation testbenches, and PYNQ-Z2 board implementation. I’m continuing my learning on both the PYNQ-Z2 and Digilent Nexys A7-100T.
Completed RTL and simulation work
- Developed Verilog modules for decoders, priority encoders, adders, and ROM-based comparators.
- Initialized ROM contents with
$readmemband explored Vivado’s Block Memory Generator IP and COE initialization. - Wrote a testbench exercising all 16 input combinations of a 2-bit ROM comparator and inspected its outputs in Vivado behavioral simulation.
Board implementation
For a 2-to-1 multiplexer, I assigned PYNQ-Z2 pins with XDC constraints, ran synthesis and implementation, generated a bitstream, and programmed the board. I verified the switch-to-LED behavior on the hardware.
I also built a Zynq processing-system design in Vivado IP Integrator, generated the HDL wrapper and bitstream, and used the PYNQ-Z2 setup to control board LEDs.
Current learning approach
I’m using three resources to structure my learning across RTL design, FPGA implementation, and verification:
- Parallel Programming Labs — structured Verilog and FPGA/SoC exercises that I’m following on the PYNQ-Z2.
- The FPGA Programming Handbook, 2nd edition, by Frank Bruno and Guy Eschemann (ISBN-13: 978-1-80512-559-4) — my guide for RTL design, FPGA architecture, and implementation exercises on the Nexys A7-100T.
- SystemVerilog for Verification, 3rd edition, by Chris Spear and Greg Tumbush, for testbench development, simulation, and verification methodology.
My focus is to progress from individual logic blocks to more complete, verified FPGA designs, documenting simulation results and hardware behavior along the way.